1. Technical Field
The present invention relates to integrated circuit design methods in general, and, in particular, to a method for assigning clock-gated circuits within an integrated circuit design. Still more particularly, the present invention relates to a method for converting globally clock-gated circuits to locally clock-gated circuits within an integrated circuit design.
2. Description of Related Art
A digital integrated circuit (IC) design typically employs many clock-gated circuits, such as flip-flops, latches, etc., that are periodically clocked by edges of a clock signal. Since there is a very large number (thousands or millions) of clock-gated circuits within an IC design, a single clock signal driver normally cannot directly supply a clock signal to all of the clock-gated circuits. Instead, a global clock tree having a set of buffers arranged in a tree-like network is utilized to supply clock signals to various clock-gated circuits. All circuits clocked by a global clock tree are considered as globally clock-gated circuits.
In order to ensure proper synchronization between various parts of a circuit design, each clock signal edge should reach all synchronization points at substantially the same time. Thus, the time required for a clock signal edge to travel from its source to any clock-gated circuit should be substantially the same for all paths it follows through the global clock tree. The time required for a clock signal edge to work its way through the global clock tree from its source to a globally clock-gated circuit depends on many factors, such as the lengths of conductors in the path, the number of buffers the edge must pass through, the switching delay of each buffer, the amount of attenuation of the clock signal incurs between buffer stages, and the load each buffer must drive. Accordingly, the global clock tree needs to be balanced by ensuring that all clock signal paths between any two tree levels are of substantially similar length and impedance, that all buffers at any level of the global clock tree drive the same number of buffers or globally clock-gated circuits at the next level of the global clock tree, and that all buffers on any given level have similar characteristics.
Generally speaking, global clock trees consume a relatively large amount of power. Global clock trees typically attribute to approximately 30-60% of the total power consumption of an IC design. In addition, the clocking of a global clock tree requires a rigid boundary between pipeline stages such that all logic must line up upon the boundaries. Thus, the ability to improve performance either in the current pipeline stage or in the next pipeline stage becomes locked to the clock boundary. The present disclosure provides a method for reducing overall clocking power consumption of an IC design such that additional flexibility in clock management can be achieved.